Hardware Implementation of the ηT Pairing in Characteristic 3

Recently, there have been many proposals for secure and novel cryptographic protocols that are built on bilinear pairings. The ηT pairing is one such pairing and is closely related to the Tate pairing. In this paper we consider the efficient hardware implementation of this pairing in characteristic 3. All characteristic 3 operations required to compute the pairing are outlined in detail. An efficient, flexible and reconfigurable processor for the ηT pairing in characteristic 3 is presented and discussed. The processor can easily be tailored for a low area implementation, for a high throughput implementation, or for a balance between the two. Results are provided for various configurations of the processor when implemented over the field F397 on an FPGA. As far as we are aware, the processor returns the first characteristic 3 ηT pairing in hardware that includes a final exponentiation to a unique value.